View ICE2QS0311_4582424.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ice2qs03 quasi-resonant pwm controller never stop thinking. power management & supply datasheet,version 2.1, april 21, 2011
edition april 21, 2011 published by ? infineon technologies ag ? 81726 mnchen, germany ? infineon technologies ag 4/21/11. ? all rights reserved. attention please! the information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hints giv en herein, any typical values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices pl ease contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http:// www.infineon.com coolmos ? , coolset ? are trademarks of infineon technologies ag. ice2qs03 ? revision history: april 21, 2011 datasheet previous version: 2.0 page17 test condition iout changed from 20ma to 10ma
version 2.1 3 april 21, 2011 ice2qs03 typical application circuit quasi-resonant pwm controller product highlight ? active burst mode for low standby power ? digital frequency reduction for better overall system efficiency ? integrated power cell for ic self-power supply features ? quasiresonant operation till very low load ? active burst mode operation at light/no load for low standby input power (< 100mw) ? digital frequency reduction with decreasing load ? power cell for vcc pre-charging with constant current ? built-in digital soft-start ? foldback correction and cycle-by-cycle peak current limitation ? auto restart mode for vcc overvoltage protection ? auto restart mode for vcc undervoltage protection ? auto restart mode for openloop/overload protection ? latch-off mode for adjustable output overvoltage protection ? latch-off mode for short-winding protection description ice2qs03 is a quasi-resonant pwm controller optimized for off-line switch power supply applications such as lcd tv, crt tv and notebook adapter. the digital frequency reduction with decreasing load enables a quasi-resonant operation till very low load. as a result, the overall system efficiency is significantly improved compared to other conventional solutions. the active burst mode operation enables an ultra-low power consumption at standby mode with small and controllable output voltage ripple. based on the bicmos technology, the product has a wide operation range (up to 26v) of ic power supply and lower power consumption. the numerous protection functions give a full protection of the power supply system in failure situations. all of these make the ice2qs03 an outstanding controller for quasi-resonant flyback converter in the market. type package ice2qs03 pg-dip-8-6 85 ~ 265vac snubber c bus d r1 ~d r4 power cell gnd fb hv vcc zc gate cs power management digital process block active burst mode protection block current mode control control unit gate driver zero crossing detection current limitation ice2qs03 r cs tl431 optocoupler r b1 r b2 r c1 c c1 c c2 r ovs2 r ovs1 c vcc r vcc r zc2 r zc1 c zc d vcc w p w s w a d o c o l f c f v o c fb c ps c ds q1
quasi-resonant pwm controller ice2qs03 table of contents page version 2.1 4 april 21, 2011 1 pin configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1 pin configuration with pg-dip-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2 package pg-dip-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.3 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2 representative block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1 vcc pre-charging and typical vcc voltage during start-up . . . . . . . . . . .7 3.2 soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3 normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3.1 digital frequency reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3.1.1 up/down counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3.1.2 zero crossing (zc counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3.2 ringing suppression time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3.3 switch off determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4.1 foldback point correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5 active burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.5.1 entering active burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.5.2 during active burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.5.3 leaving active burst mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.6 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.2 internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.3 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3.4 current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3.5 soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3.6 foldback point correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3.7 digital zero crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.3.8 active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.3.9 protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.3.10 gate drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 5 outline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
quasi-resonant pwm controller ice2qs03 pin configuration and functionality version 2.1 5 april 21, 2011 1 pin configuration and functionality 1.1 pin configuration with pg-dip- 8 pin symbol function 1 zc zero crossing 2 fb feedback 3 cs current sense 4 hv high voltage input 5 hv high voltage input 6 gate gate drive output 7 vcc controller supply voltage 8 gnd controller ground -6 1.2 package pg-dip-8 1 6 7 8 4 3 2 5 gnd zc fb cs vcc gate hv hv -6 figure 1 pin configuration pg-dip-8-6(top view) 1.3 pin functionality zc (zero crossing) at this pin, the voltage from the auxiliary winding after a time delay circuit is applied. internally, this pin is connected to the zero-crossing detector for switch-on determination. additionally, the output overvoltage detection is realized by comparing the voltage vzc with an internal preset threshold. fb (feedb ack) normally, an external capacitor is connected to this pin fo r a smooth voltage v fb . internally, this pin is connected to the pwm signal generator for switch-off determination (together with the current sensing signal), the digital signal processing for the frequency reduction with decreasing load during normal operation, and the active burst mode controller for entering active burst mode operation determination and burst ratio control during active burst mode operation. additionally, the open-loop / over-load protection is implemented by monitoring the voltage at this pin. cs (cu rrent sense) this pin is connected to the shunt resistor for the p rimary current sensing, externally, and the pwm signal generator for switch-off determination (together with the feedback voltage), internally. moreover, short- winding protection is realised by monitoring the voltage vcs during on-time of the main power switch. gate (gate drive output) this output signal drives the external main power switch, which is a power mosfet in most case. hv (hig h voltage) the pin hv is connected to the bus voltage, externally, and to the power cell, internally. the current through t his pin pre-charges the vcc capacitor with constant current once the supply bus voltage is applied. vcc (p ower supply) vcc pin is the positive supply of the ic. the operating r ange is between v vccoff and v vccovp . gnd (g round) this is the common ground of the controller.
quasi-resonant pwm controller ice2qs03 representative block diagram version 2.1 6 april 21, 2011 2 representative block diagram 1 g2 1 g7 r sq latched protect r sq autorestart protect protection r fb 1 g3 25k o 2pf d1 & g1 & g5 1 g4 t beb & g6 active burst block fb c8 v fbeb c9 v fbbon c10 v fbboff c3 v zcrs c2 v zcovp delay t zcovp f sb osc active burst mode t count c1 v zcc zc up/down counter zc counter clk comparator soft-start ringing suppression count=7 v ref r s q g8 & g9 startup cell hv cs vcc gate drive g pwm pwm op current mode pwm comparator v pwm q voltage reference undervoltage lockout 18v 10.5 10us internal bias power management depl. coolmos ? t onmax c7 v fbzl c6 v fbzh c5 v fbr1 c4 v fbolp t olp_b regulation current limiting 10k o d2 leading edge blanking t leb 1pf foldback correction delay t cssw c13 v csb c14 v cssw c15 pwm control zero crossing gate drive gnd en c12 v vccovp t offmax otp gate figure 2 representative block diagram
quasi-resonant pwm controller ice2qs03 functional description version 2.1 7 april 21, 2011 3 functional description 3.1 vcc pre-charging and typical vcc voltage du ring start-up in ice2qs03, a high voltage startup cell is integrated. as shown in figure 2, the start cell consists of a high voltage device and a controller, whereby the high voltage device is controlled by the controller. the startup cell provides a pre-charging of the vcc capacitor till vcc voltage reaches the vcc turned-on threshold v vccon and the ic begins to operate. once the mains input voltage is applied, a rectified volt age shows across the capacitor c bus . the high voltage device provides a current to charge the vcc capacitor c vcc . before the vcc voltage reaches a certain value, the amplitude of the current through the high voltage device is only determined by its channel resistance and can be as high as several ma. after the vcc voltage is high enough, the controller controls the high voltage device so that a constant current around 1ma is provided to charge the vcc capacitor further, until the vcc voltage exceeds the turned-on threshold v vccon . as shown as the time phase i in figure 3, the vcc voltage increase near linearly and the charging speed is independent of the mains voltage level. v vccon v vcc v vccoff t1 t t2 iiiiii figure 3 vcc voltage at start up the time taking for the vcc pre-charging can then be ap proximately calculated as: [1] where i vcccharge2 is the charging current from the startup cell which is 1.05ma, typically. exceeds the vcc voltage the turned-on threshold v vccon of at time t 1 , the startup cell is switched off, and the ic begins to operate with a soft-start. due to power consumption of the ic and the fact that still no energy from the auxiliary winding to charge the vcc capacitor before the output voltage is built up, the vcc voltage drops (phase ii). once the output voltage is high enough, the vcc capacitor receives then energy from the auxiliary winding from the time point t 2 on. the vcc then will reach a constant value depending on output load. 3.2 soft-start at the time t on , the ic begins to operate with a soft-start. by this soft-start the swit ching stresses for the switch, diode and transformer are minimised. the soft-start implemented in ice2qs03 is a digital time-based function. the preset soft-start time is 12ms with 4 steps. if not limited by other functions, the peak voltage on cs pin will increase step by step from 0.32v to 1v finally. t on 3691 2 0.32 0.49 0.66 0.83 1.00 vcs_sst (v) time(ms) figure 4 maximum current sense voltage during so ftstart 3.3 normal operation the pwm controller during normal operation consists of a digital signal processing circuit including an up/ down counter, a zero-crossing counter (zc counter) and a comparator, and an analog circuit including a current measurement unit and a comparator. the switch-on and -off time points are each determined by the digital circuit and the anal og circuit, res pectively. as input information for the switch-on determination, the zero-crossing input signal and the value of the up/down counter are needed, while the feedback signal v fb and the current sensing signal v cs are necessary for the switch-off determination. details about the full operation of the pwm controller in normal operation are illustrated in the following paragraphs. 3.3.1 digital frequency reduction as mentioned above, the digital signal processing circui t consists of an up/dow n counter, a zc counter and a comparator. these three parts are key to implement digital frequency reduction with decreasing load. in addition, a ringing suppression time controller is implemented to avoid mistriggering by the high frequency oscillation, when the output voltage is very low under conditions such as soft start or output short circuit . functionality of these parts is described as in the following. w 9 9&&rq & yff ? , 9&&fk h duj ------------------------------------------ - =
quasi-resonant pwm controller ice2qs03 functional description version 2.1 8 april 21, 2011 3.3.1.1 up/down counter the up/down counter stores the number of the zero crossing to be ignored before the main power switch is switched on after demagnetisation of the transformer. this value is fixed according to the feedback voltage, v fb , which contains information about the output power. indeed, in a typical peak current mode control, a high output power results in a high feedback voltage, and a low output power leads to a low regulation voltage. hence, according to v fb , the value in the up/ down counter is changed to vary the power mosfet off-time according to the output power. in the following, the variation of the up/down counter value according to the feedback voltage is explained. the feedback voltage v fb is internally compared with three threshold voltages v rl , v rh and v rm , at each clock period of 48ms. the up/down counter counts then upward, keep unchanged or count downward, as shown in table 1. table 1 operation of the up/down counter v fb up/down counter ac tion always lower than v fbzl count upwards till 7 once higher than v fbzl , but always lower than v fbzh stop counting, no value changing once higher than v fbzh , but always lower than v fbr1 count downwards till 1 once higher than v fbr1 set up/down counter to 1 in the ice2qs03, the number of zero crossing is limit ed to 7. therefore, the counter varies between 1 and 7, and any attempt beyond this range is ignored. when v fb exceeds v fbr1 voltage, the up/down counter is initialised to 1, in order to allow the system to react rapidly to a sudden load increase. the up/down counter value is also intialised to 1 at the start-up, to ensure an efficient maximum load start up. figure 5 shows some examples on how up/down counter is chan ged according to the feedback voltage over time. the use of two different thresholds v fbzl and v fbzh to count upward or downward is to prevent frequency jittereing when the feedback voltage is close to the threshold point. however, for a stable operation, these two thresholds must not be affected by the foldback current limitation (see section 3.4.1), which limits the v cs voltage. hence, to prevent such situation, the threshold voltages, v fbzl and v fbzh , are changed internally depending on the line voltage levels. 1 case 3 case 2 case 1 up/down counter n n+1 n+2 n+2 n+2 n+2 n+1 n n-1 4 5 6 6 6 6 5 4 3 1 1 2 3 4 4 4 4 3 2 1 7 7 7 7 7 7 6 5 4 t t v fb v fbr1 v fbzh v fbzl clock t=48ms 1 figure 5 up/down counter operation 3.3.1.2 zero crossing (zc counter) in the system, the voltage from the auxiliary winding is a pplied to the zero-crossing pin through a rc network, which provides a time delay to the voltage from the auxiliary winding. internally, this pin is connected to a clamping network, a zero-crossing detector, an output overvoltage detector and a ringing suppression time controller. during on-state of the power switch a negative voltage a pplies to the zc pin. through the internal clamping network, the voltage at the pin is clamped to certain level. the zc counter has a minimum value of 0 and ma ximum value of 7. after the internal mosfet is turned off, every time when the falling voltage ramp of on zc pin crosses the 100mv threshold, a zero crossing is detected and zc counter will increase by 1. it is reset every time after the gate output is changed to high. the voltage v zc is also used for the output overvoltage protection. once the voltage at this pin is higher than the threshold v zcovp during off-time of the main switch, the ic is latched off after a fixed blanking time. to achieve the switch-on at voltage valley, the voltage from the auxiliary winding is f ed to a time delay network (the rc network consists of d zc , r zc1 , r zc2 and c zc as shown in typical application circuit) before it is applied to the zero-crossing detector through the zc pin. the needed time delay to the main oscillation signal ' t should be approximately one fourth of the oscillation period (by transformer primary inductor and drain- source capacitor) minus the propagation delay from
quasi-resonant pwm controller ice2qs03 functional description version 2.1 9 april 21, 2011 thedetected zero-crossing to the switch-on of the main switch t delay , theoretically: [2] this time delay should be matched by adjusting the time constant of the rc network which is calculated as: [3] 3.3.2 ringing suppression time after mosfet is turned off, there will be some oscillation on v ds , which will also appear on the voltage on zc pin. to avoid that the mosfet is turned on mistriggerred by such oscillations, a ringing suppression timer is implemented. the timer is dependent on the voltage v zc . when the voltage v zc is lower than the threshold v zcrs , a longer preset time applies, while a shorter time is set when the voltage v zc is higher than the threshold. 3.3.2.1 switch on determination after the gate drive goes to low, it can not be changed to high during ring suppression time. after ring suppression time, the gate drive can be turned on when the zc counter value is higher or equal to up/down counter value. however, it is also possible that the oscillation between primary inductor and drain-source capacitor damps very fast and ic can not detect enough zero crossings and zc counter value will not be high enough to turn on the gate drive. in this case, a maximum off time is implemented. after gate drive has been remained off for the period of t offmax , the gate drive will be turned on again regardless of the counter values and v zc . this function can effectively prevent the switching frequency from going lower than 20khz, otherwise which will cause audible noise, during start up. 3.3.3 switch off determination in the converter system, the primary current is sensed by an external shunt resi stor, which is connected between low-side terminal of the main power switch and the common ground. the sensed voltage across the shunt resistor v cs is applied to an internal current measurement unit, and its output voltage v 1 is compared with the regulation voltage v fb . once the voltage v 1 exceeds the voltage v fb , the output flip-flop is reset. as a result, the main power switch is switched off. the relationship between the v 1 and the v cs is described by: [4] to avoid mistriggering caused by the voltage spike across the shunt resistor at the turn on of the main power switch, a leading edge blanking time, t leb , is applied to the output of the comparator. in other words, once the gate drive is turned on, the minimum on time of the gate drive is the leading edge blanking time. in addition, there is a maximum on time, t onmax , limitation implemented in the ic. once the gate drive has been in high state longer than the maximum on time, it will be turned off to prevent the switching frequency from going too low because of long on time. 3.4 current limitation there is a cycle by cycle current limitation realized by the current limit comparator to provide an overcurrent detection. the source current of the mosfet is sensed via a sense resistor r cs . by means of r cs the source current is transformed to a sense voltage v cs which is fed into the pin cs. if the voltage v cs exceeds an internal voltage limit, adjusted according to the mains voltage, the comparator immediately turns off the gate drive. to prevent the current limitation process from distortions caused by leading edge spikes, a leading edge blanking time (t leb ) is integrated in the current sensing path. a further comparator is implemented to detect dangerous current levels (v cssw ) which could occur if one or more transformer windings are shorted or if the secondary diode is shorted. to avoid an accidental latch off, a spike blanking time of t cssw is integrated in the output path of the comparator . 3.4.1 foldback point correction when the main bus voltage increases, the switch on time becomes shorter and therefore the operating frequency is also increased. as a result, for a constant primary current limit, the maximum possible output power is increased, which the converter may have not been designed to support. to avoid such a situation, the internal foldback point correction circuit varies the v cs voltage limit according to the bus voltage. this means the v cs will be decreased when the bus vo ltage increases. to keep a constant maximum input power of the converter, the ?? ? ??? ? ? ????? ? ?? ? ?? ? ??? ? ??? ? ? ??? ? ??? ? ? ? ??? ? ?? ????
quasi-resonant pwm controller ice2qs03 functional description version 2.1 10 april 21, 2011 required maximum v cs versus various input bus voltage can be calculated, which is shown in figure 6 . 0.6 0.7 0.8 0.9 1 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400 vin(v) vcs-max(v) figure 6 variation of the vcs limit voltage according to the i zc current according to the typical application circuit, when mos fet is turned on, a negative voltage proportional to bus voltage will be coupled to auxiliary winding. inside ice2qs03, an internal circuit will clamp the voltage on zc pin to nearly 0v. as a result, the current flowing out from zc pin can be calculated as [5] when this current is higher than i zc_1 , the amount of current exceeding this threshold is used to generate an offset to decrease the maximum limit on v cs . since the ideal curve shown in figure 6 is a nonlinear one, a digital block in ice2qs03 is implemented to get a be tter control of maximum output power. additional advantage to use digital circuit is the production tolerance is smaller compared to analog solutions. the typical maximum limit on v cs versus the zc current is shown in figure 7 . 0.6 0.7 0.8 0.9 1 300 500 700 900 1100 1300 1500 1700 1900 2100 iz c(ua) vcs-max(v) figure 7v cs-max versus i zc 3.5 active burst mode operation at light load condition, the ic enters active burst mode operation to minimize the power consumption. details about active burst mode operation are explained in the following paragraphs. 3.5.1 entering active burst mode operation for determination of entering active burst mode o peration, three conditions apply: ? the feedback voltage is lower than the threshold of v fbeb (1.25v). accordingly, the peak current sense voltage across the shunt resistor is 0.17; ? the up/down counter is 7; and ? a certain blanking time (t beb ). once all of these conditions are fulfilled, the active b urst mode flip-flop is set and the controller enters active burst mode operation. this multi-condition determination for entering active burst mode operation prevents mistriggering of entering active burst mode operation, so that the controller enters active burst mode operation only when the output power is really low during the preset blanking time. 3.5.2 during active burst mode operation after entering the active burst mode the feedback vol tage rises as v out starts to decrease due to the inactive pwm section. one comparator observes the feedback signal if the voltage level v bh (3.6v) is exceeded. in that case the internal circuit is again activated by the internal bias to start with swtiching. turn-on of the power mosfet is triggered by the t imer. the pwm generator for active burst mode operation composes of a timer with a fixed frequency of 52khz, typically, and an analog comparator. turn-off is resulted by comparison of the voltage signal v 1 with an internal threshold, by which the voltage across the shunt resistor v csb is 0.34v, accordingly. a turn-off can also be triggered by the maximal duty ratio controller which sets the maximal duty ratio to 50%. in operation, the output flip-flop will be reset by one of these signals which come first. if the output load is still low, the feedback signal d ecreases as the pwm section is operating. when feedback signal reaches the low threshold v bl (3.0v), the internal bias is reset again and the pwm section is disabled until next time regultaion siganl increases beyond the v bh threshold. if working in active burst mode the feedback signal is changing like a saw tooth between 3.0v and 3.6v shown in figure 7. 3.5.3 leaving active burst mode operation the feedback voltage immediately increases if there is a high load jump. this is observed by one comparator. as the current limit is 34% during active burst mode a certain load is needed so that feedback voltage can exceed v lb (4.5v). after leaving active busrt mode, maximum current can now be provided to stabilize v o . in addition, the up/down counter will be set to 1 , =& 9 %86 1 d 5 =& 1 3 ------------------------ - =
quasi-resonant pwm controller ice2qs03 functional description version 2.1 11 april 21, 2011 immediately after leaving active burst mode. this is helpful to decrease the output voltage undershoot. v fbeb v fbbon v fblb v fb t v csb 1.0v v cs v vccoff v vcc t t v o t v fbboff max. ripple < 1% blanking window (t beb ) current limit level during active burst mode leaving active burst mode entering active burst mode figure 8 signals in active burst mode 3.6 protection functions the ic provides full protection functions. the following table summarizes these protection functions. table 2 vcc overvoltage auto restart mode vcc undervoltage auto restart mode overload/open loop auto restart mode over temperature auto restart mode output overvoltage latched off mode short winding latched off mode protection features during operation, the vcc voltage is continuously moni tored. in case of an under- or an over-voltage, the ic is reset and the main power switch is then kept off. after the vcc voltage falls below the threshold v vccoff , the startup cell is activated. the vcc capacitor is then charged up. once the voltage exceeds the threshold v vccon , the ic begins to operate with a new soft-start. in case of open control loo p or output over load , the feed back voltage will be pulled up . after a blanking time of 24ms, the ic enters auto-restart mode. the blanking time here enables the converter to provide a high power in case the increase in v fb is due to a sudden load increase. during off-time of the power switch, the voltage at the zero-crossing pin is monitored for output over-voltage detection. if the voltage is higher than the preset threshold v zcovp , the ic is latched off after the preset blanking time. if the junction temperature of ic exceeds 140 q c , t he ic enter into autorestart mode. if the voltage at the current sensing pin is higher than t he preset threshold v cssw during on-time of the power switch, the ic is latched off. this is short-winding protection. during latch-off protection mode, when the vcc vol tage drops to 10.5v,the startup cell is activated and the vcc voltage is charged to 18v then the startup cell is shut down again and repeats the previous procedure. there is also an maximum on time limitation inside i ce2qs03. once the gate voltage is high longer than t onmax , it is turned off immediately.
quasi-resonant pwm controller ice2qs03 electrical characteristics version 2.1 12 april 21, 2011 4 electrical characteristics note: all voltages are measured with respect to ground (pin 8). the voltage levels are valid if other ratings are not violated. 4.1 absolute maximum ratings parameter symbol limit values unit remarks min. max. hv voltage v hv - 500 v vcc supply voltage v vcc -0.3 27 v fb voltage v fb -0.3 5.0 v zc voltage v zc -0.3 5.0 v cs voltage v cs -0.3 5.0 v gate voltage v out -0.3 27 v maximum current out from zc pin i zcmax 3 - ma junction temperature t j -40 125 q c storage temperature t s -55 150 q c thermal resistance junction -ambient r thja - 90 k/w pg-dip-8 esd capability (incl. drain pin) v esd - 2 kv human body model 1) 1) according to eia/jesd22-a114-b (discharging a 100pf capacitor through a 1.5k : series resistor) note: absolute maximum ratings are defined as rating s, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capacitor that will be connected to pin 7 ( v cc) is discharged before assembling the application circuit. 4.2 operating range note: within the operating range the ic operates as described in the functional description. parameter symbol limit values unit remarks min. max. vcc supply voltage v vcc v vccoff v vccovp v junction temperature of cont roller t jcon -25 125 c
quasi-resonant pwm controller ice2qs03 electrical characteristics version 2.1 13 april 21, 2011 4.3 characteristics 4.3.1 supply section note: the electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range t j from ? 25 q c t o 125 q c. typical values represent the median values, which are related to 25c. if not otherwise stated, a supply voltage of v cc = 18 v is assumed. parameter symbol limit values unit test condition min. typ. max. start up current i vccstart - 300 550 p a v vcc =v vccon -0.2v vcc charge current i vcccharge1 - 5.0 - ma v vcc = 0v i vcccharge2 0.8 - - ma v vcc = 1v i vcccharge3 - 1.0 - ma v vcc =v vccon -0.2v maximum input current of startup cell and coolmo s ? i drainin - - 2 ma v vcc =v vccon -0.2v leakage current of startup cell and coolmo s ? i drainleak - 0.2 50 p a v drain = 610v at t j =100c supply current in normal op eration i vccnm - 1.5 2.3 ma output low supply current in auto restart mode with inactive ga te i vccar - 300 - p a i fb = 0a supply current in latch-off mode i vcclatch - 300 - p a supply current in burst mode with in active gate i vccburst - 500 950 p a v fb = 2.5v, exclude the current flowing out from fb pin vcc turn-on threshold v vccon 17.0 18.0 19.0 v vcc turn-off threshold v vccoff 9.8 10.5 11.2 v vcc turn-on/off hysteresis v vcchys - 7.5 - v 4.3.2 internal voltage reference parameter symbol limit values unit test condition min. typ. max. internal reference voltage v ref 4.80 5.00 5.20 v measured at pin fb i fb =0
quasi-resonant pwm controller ice2qs03 electrical characteristics version 2.1 14 april 21, 2011 4.3.3 pwm section parameter symbol limit values unit test condition min. typ. max. feedback pull-up resistor r fb 14 23 33 k: pwm-op gain g pwm 3.18 3.3 - - offset for voltage ramp v pwm 0.63 0.7 - v maximum on time in normal op eration t onmax 22 30 41 p s 4.3.4 current sense parameter symbol limit values unit test condition min. typ. max. peak current limitation in normal op eration v csth 0.97 1.03 1.09 v leading edge blanking time t leb 200 330 460 ns peak current limitation in a ctive burst mode v csb 0.29 0.34 0.39 v 4.3.5 soft start parameter symbol limit values unit test condition min. typ. max. soft-start time t ss 8.5 12 - ms soft-start time step t ss_s 1) 1) the parameter is not subjected to production test - verified by design/characterization - 3 - ms internal regulation voltage at fir st step v ss1 1) - 1.76 - v internal regulation voltage step at soft start v ss_s 1) - 0.56 - v 4.3.6 foldback point correction parameter symbol limit values unit test condition min. typ. max. zc current first step threshold i zc_fs 0.35 0.5 0.621 ma zc current last step threshold i zc_ls 1.8 2 2.2 ma cs threshold minimum v csmf - 0.66 - v i zc =2.2ma, v fb =3.8v
quasi-resonant pwm controller ice2qs03 electrical characteristics version 2.1 15 april 21, 2011 4.3.7 digital zero crossing parameter symbol limit values unit test condition min. typ. max. zero crossing threshold voltage v zcct 50 100 170 mv ringing suppression threshold v zcrs - 0.7 - v minimum ringing suppression tim e t zcrs1 1.8 2.5 3.4 p s v zc > v zcrs maximum ringing suppression time t zcrs2 - 25 - p s v zc < v zcrs threshold to set up/down counter to one v fbr1 3.9 v threshold for downward coun ting at low line v fbzhl 3.2 v threshold for upward counting at low line v fbzll 2.5 v threshold for downward coun ting at hig line v fbzhh 2.9 v threshold for upward counting at highline v fbzlh 2.3 v zc current for ic switch t hreshold to high line i zcsh - 1.3 - ma zc current for ic switch thresho ld to low line i zcsl - 0.8 - ma counter time 1) 1) the parameter is not subjected to production test - verified by design/characterization t count 48 ms maximum restart time in normal op eration t offmax 30 42 57.5 p s
quasi-resonant pwm controller ice2qs03 electrical characteristics version 2.1 16 april 21, 2011 4.3.8 active burst mode parameter symbol limit values unit test condition min. typ. max. feedback voltage for entering a ctive burst mode v fbeb - 1.25 - v minimum up/down value for en tering active burst mode n zc_abm 7 blanking time for entering active bu rst mode t beb - 24 - ms feedback voltage for leaving a ctive burst mode v fblb - 4.5 - v feedback voltage for burst-on v fbbon - 3.6 - v feedback voltage for burst-off v fbboff 3.0 v fixed switching frequency in active burst mode f sb - 52 - khz max. duty cycle in active burst mode d maxb - 0.5 - 4.3.9 protection parameter symbol limit values unit test condition min. typ. max. vcc overvoltage threshold v vccovp 24.0 25.0 26.0 v over load or open loop det ection threshold for olp protection at fb pin v fbolp 4.5 v over load or open loop pr otection blanking time t olp_b 20 30 44 ms output overvoltage detection t hreshold at the zc pin v zcovp 3.55 3.7 3.84 v blanking time for output over voltage protection t zcovp 100 p s threshold for short winding pr otection v cssw 1.63 1.68 1.78 v blanking time for short-windding pr otection t cssw - 190 - ns over temperature protection 1) t jcon - 140 - 0 c note: the trend of all the voltage levels in the control unit is the same regarding the deviation except v vccovp
quasi-resonant pwm controller ice2qs03 electrical characteristics version 2.1 17 april 21, 2011 4.3.10 gate drive parameter symbol limit values unit test condition min. typ. max. output voltage at logic low v gatelow - 1.0 v v vcc =18v i out = 10ma output voltage at logic high v gatehigh 9.0 10.0 v v vcc =18v i out = -10ma output voltage active shut down v gateasd 1.0 v v v vcc = 7v i out = 10ma rise time t rise - 117 - ns c out = 1.0nf v gate = 2v ... 8v fall time t fall - 27 - ns c out = 1.0nf v gate = 8v ... 2v
quasi-resonant pwm controller ice2qs03 outline dimension version 2.1 18 april 21, 2011 5 outline dimension pg-dip-8-6 / pg-dip-8-9 (leadfree plastic dual in-line outline) figure 9 pg-dso-8 (pb-free lead plating plastic dual small outline) dimensions in mm
qualit?t hat fr uns eine umfassende bedeutung. wir wollen allen ihren ansprchen in der bestm?glichen weise gerecht werden. es geht uns also nicht nur um die produktqualit?t ? unsere anstrengungen gelten gleicherma?en der lieferqualit?t und logistik, dem service und support sowie allen sonstigen beratungs- und betreuungsleistungen. dazu geh?rt eine bestimmte geisteshaltung unserer mitarbeiter. total quality im denken und handeln gegenber kollegen, lieferanten und ihnen, unserem kunden. unsere leitlinie ist jede aufgabe mit ?null fehlern? zu l?sen ? in offener sichtweise auch ber den eigenen arbeitsplatz hinaus ? und uns st?ndig zu verbessern. unternehmensweit orientieren wir uns dabei auch an ?top? (time optimized processes), um ihnen durch gr??ere schnelligkeit den entscheidenden wettbewerbsvorsprung zu verschaffen. geben sie uns die chance, hohe leistung durch umfassende qualit?t zu beweisen. wir werden sie berzeugen. quality takes on an allencompassing significance at semiconductor group. for us it means living up to each and every one of your demands in the best possible way. so we are not only concerned with product quality. we direct our efforts equally at quality of supply and logistics, service and support, as well as all the other ways in which we advise and attend to you. part of this is the very special attitude of our staff. total quality in thought and deed, towards co- workers, suppliers and you, our customer. our guideline is ?do everything with zero defects?, in an open manner that is demonstrated beyond your immediate workplace, and to constantly improve. throughout the corporation we also think in terms of time optimized processes (top), greater speed on our part to give you that decisive competitive edge. give us the chance to prove the best of performance through the best of quality ? you will be convinced. http://www.infineon.com total quality management published by infineon technologies ag

▲Up To Search▲

Price & Availability of ICE2QS0311

	To Download ICE2QS0311 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .